The present disclosure generally relates to stacked surface arrangements, and more particularly, to soldering between stacked surface arrangements.
Lead-free solder joining of large dies to an organic or ceramic substrate can result in high stresses on the chip internal wiring due to the high coefficient of thermal expansion (CTE) mismatch between the die and substrate. Low-k dielectrics can fracture due to these large stresses, which maximize during the cooling cycle of the joining process. One of the ways to determine dielectric failure after chip joining is through the use of acoustic micro imaging, where any fracture is reflected as a white area, or as it is commonly referred, a white bump (see FIGS. 1A and 1B). Formation of white bumps can indicate that stresses between a chip and a substrate are so high that fracture in the interlayer dielectric in the vicinity of the solder bump occurs.
There are several ways to reduce the CTE effect, for example differential heating and cooling during thermal compression bonding. However, this requires individual chip alignment and joining and is more costly than mass reflow.